Up to now, a memory cell array of a flash memory is two-dimensionally formed on a surface of a semiconductor substrate to perform miniaturization and multi-levelization, thereby advancing an increase in capacity and a reduction in costs. However, in recent years, because flash memories approach the limit of the miniaturization, a memory with a novel structure is required for the purpose of further promoting the increase in the capacity and the reduction in the costs in the future. A three-dimensional memory cell array is expected to continue the increase in the capacity and the reduction in the costs even after having reached the miniaturization, and is actively being researched at present. For example, NPL 1 discloses a technique of three-dimensionally integrating NAND flash memories together, that is, a technique in which a plurality of through-holes that penetrates through all layers of a stacked structure in which gate electrode material and insulator films are alternately stacked in plural number together is formed by batch processing, and a charge trap film and a channel layer are formed and processed inside of the through-holes to form memory cells.
PTL 1 (JP-2008-160004) discloses a technique in which resistance random access memories are three-dimensionally integrated together, that is, a plurality of through-holes that penetrates through all layers of a stacked structure in which gate electrode material and insulator films are alternately stacked in plural number together is formed by batch processing, and a gate insulator film, a channel layer, and a variable resistance material layer are formed and processed inside of the through-holes to form the memory cells.
Also, PTL 2 (JP-A-2008-181978) discloses a technique in which a stacked film in which electrode material and insulator films are alternately stacked in plural number together is formed between lines orthogonal to each other in a cross point memory, a plurality of through-holes that penetrates through all layers of the stacked film is formed by batch processing, and thereafter a selective device material, a memory material and vertical lines are formed inside of the through-holes to form the memory cells.
In the memory cell arrays of NPL 1, and PTL 1 and PTL 2, since an increase in the number of processes is small even if the number of stacks is increased to provide the larger capacity, those memory cell arrays are suitable for the cost reduction. On the other hand, a memory cell size of a silicon substrate projection plane is 6×F2 (F is a minimum feature size), which is larger than 4×F2 of the two-dimensional flash memory formed on the silicon substrate. This is because select transistors necessary to select the individual memory cells from the three-dimensionally integrated memory cell array for operation need to be of a structure including a channel layer formed in a hole opened in a sidewall of a stripe-shaped gate electrode, and for that reason, an area of 6×F2 is necessary. PTL 3 (JP-A-2009-4517) discloses a technique in which the number of processes is increased to bring the select transistors into a double layer structure, and the memory cell size of the silicon substrate projection plane is set to 4×F2.
PTL 4 (JP-A-2007-180389) discloses a technique in which, in the flash memory, as a way of processing the stacked film in which the gate electrode material and the insulator films are alternately stacked in plural number together, not the through-holes are opened, but stripe-shaped grooves are formed in the stacked film, and the charge trap film and the channel film are formed and processed inside of the grooves to form the memory cells.
The variable resistance memory of the above PTL 1 is researched as a memory more suitable for miniaturization than the flash memory, and as one example of the variable resistance memory, a phase change memory using a chalcogenide material for a recording material is actively researched. A memory structure of the phase change memory is that the recording material is sandwiched between metal electrodes. The phase change memory represents a variable resistance memory that stores information with the use of a fact that the recording material between the electrodes has a different resistance state.
The phase change memory stores information with the use of a fact that a resistivity of the phase change material such as Ge2, Sb2, or Te5 is different between an amorphous state and a crystal state. The phase change material is high in resistance in the amorphous state, and low in the resistance in the crystal state. Accordingly, read is conducted by giving a voltage difference to both ends of an element, measuring a current flowing in the element, and discriminating a high resistance state and a low resistance state of the element.
In the phase change memory, an electric resistance of the phase change film is changed into a different state by a Joule heat generated by a current to program. Reset operation, that is, the operation of changing the phase change material into the amorphous state of the high resistance is conducted by rapidly decreasing the current and rapidly cooling the phase change material after a large current has been allowed to flow in a short time to fuse the phase change material. On the other hand, set operation, that is, the operation of changing the phase change material into the crystal state of the low resistance is conducted by allowing a sufficient current to keep a crystallization temperature of the phase change material to flow for a long time. The phase change memory suits for miniaturization in principle because a current necessary to change the state of the phase change film becomes small as the miniaturization is advanced, and actively researched at present.